The present invention relates generally to analog-to-digital converters (ADC), and, more particularly, to a sub-ranging ADC analog-to-digital converter.
Data converters such as ADCs are commonly used in electronic circuits such as audio and video applications, automotive applications, and the like. The ADCs that are implemented in such applications may be flash ADCs, pipeline ADCs, successive approximation register (SAR) ADCs, or the like. Desirable features of an ADC include high conversion speed, high resolution, and low power consumption. Flash ADCs have a high conversion speed but consume a lot of power and have low resolution. SAR ADCs consume low power and have high resolution compared to flash ADCs, however, SAR ADCs have a low conversion speed. Thus, it is known to combine a flash ADC and a SAR ADC to form a sub-ranging ADC.
A conventional sub-ranging ADC 100 is shown in FIG. 1. The sub-ranging ADC 100 includes a first switch 102, a coarse ADC 104, a thermometer to binary decoder 106 (hereinafter referred to as “decoder 106”), a fixed delay circuit 108, a fine ADC 110, and an error correction circuit (ECC) 112. The ADC 100 converts an analog input signal to a digital output signal. The first switch 102 samples the analog input signal in a sampling phase of an ADC conversion cycle. Thus, the coarse ADC 104 receives the analog input signal via the first switch 102 during the sampling phase. The coarse ADC 104 is a flash ADC that performs coarse conversion to convert the analog input signal to a first digital signal in a unary code format. The first digital signal includes a first set of bits that correspond to most significant bits (MSBs) of the digital output signal.
The decoder 106 receives the first digital signal and converts it from the unary code format to a binary code format. The fixed delay circuit 108 receives the first digital signal and generates a delayed first digital signal.
The fine ADC 110, which is a SAR ADC, also receives the analog input signal and performs fine conversion to convert the analog input signal to a second digital signal. The second digital signal includes a second set of bits that correspond to the least significant bits (LSBs) of the digital output signal. The fine ADC 110 includes second and third switches 114a and 114b, first and second digital-to-analog converters (DACs) 116a and 116b, fourth and fifth switches 118a and 118b, a comparator 120, and a logic circuit 122. The first and second DACs 116a and 116b receive the analog input signal via the second and third switches 114a and 114b during the sampling phase, and also receive the first digital signal from the coarse ADC 104. The first and second DACs 116a and 116b further receive a feedback signal generated by the logic circuit.
The first and second DACs 116a and 116b generate first and second analog signals, respectively. The comparator 120 receives the first and second analog signals by way of the fourth and fifth switches 118a and 118b, respectively, and generates an intermediate signal by comparing the first and second analog signals with a reference signal (not shown). The logic circuit 122 receives the intermediate signal and successively approximates the first and second analog signals to generate the second digital signal and the feedback signal.
The error correction circuit 112 receives the delayed first digital signal and the second digital signal. The LSB of the delayed first digital signal overlaps the MSB of the second digital signal. The error correction circuit 112 compares the LSB of the delayed first digital signal with the MSB of the second digital signal to detect if an error has occurred while generating the digital output signal. If so, the error correction circuit 112 will correct the error and output the digital output signal.
The sub-ranging ADC 100 has two DACs in a pipeline architecture to avoid overlapping of the fine conversions by the first and second DACs 116a and 116b. Thus, the conversion speed as well as the resolution of the digital output signal are low. Further, the coarse and fine conversions are performed in a single phase of the ADC conversion cycle. Hence, a dedicated phase for performing the coarse and fine conversions is absent, which affects the time required to perform the coarse conversion and increases power consumption.
Accordingly, it would be advantageous to have a sub-ranging ADC that provides dedicated phases for coarse and fine conversions and has a higher conversion speed than the conventional sub-ranging ADC.